Motorola DSP96002 User Manual page 255

32-bit digital signal processor
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CMP
Operation:
S2.L - S1.L
(parallel data bus move)
Description:
Subtract the low portion of the two operands as specified in the operation column above. No result is
stored; however, the condition codes are affected as described below.
CMPG and CMP differ primarily in the definition of the CCR condition code bits LR and R. These differenc-
es are particularly useful in performing clipping operations in graphics applications. In the code segment,
the CMP instruction tests the first point of a line, X0, against X
instruction tests the second point of a line, X1, against X
Note that the line segment will be trivially accepted if A is set (and R=1), whereas the line will be trivially
rejected if
R is cleared (and A=0). This choice of accept/reject conditions was selected to permit the CCR
to be initialized by a single ORI instruction.
ORI
#$E0,CCR
MOVE
CMP
D1, D0
CMPG
D1, D0
Input Operand(s) Precision: 32-bit 2's complement integer.
Output Operand Precision: n.a.
CCR Condition Codes:
C
- Set if a borrow is generated from the MSB of the result. Cleared otherwise.
V
- Set if result overflows. Cleared otherwise.
Z
- Set if result is zero. Cleared otherwise.
N
- Set if result is negative. Cleared otherwise.
I
- Not affected.
LR
- Cleared if result is positive without overflow or zero. Cleared if result is negative
R
- Not affected. See the example for the FCMPG instruction.
MOTOROLA
Compare
X:(R0)+N0,D0.L
X:(R0)-N0, D0.L
with overflow. Not affected otherwise. See the example for the FCMPG instruction.
DSP96002 USER'S MANUAL
Assembler Syntax:
CMP
S1,S2
(move syntax - see the MOVE in-
struction description.)
and sets LR according ly; the FCMPG
min
and sets
R depending on the condition of LR.
min
Y:(R4)+,D1.S
CMP
;SET A,
R, LR – i. e.,
;assume line is initially
;accepted and not rejected.
;get X0, X
min
;X0-X
, get X1
min
;X1=X
min
A - 67

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