Motorola DSP96002 User Manual page 771

32-bit digital signal processor
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.
MOVE EXPONENT RANGE
IN
(UNBIASED)
TYPE
SP
e= 128
Fraction=
.0xx...xx
SP
e= 128
Fraction=
.1xx...xx
SP
e= 128
Fraction=
.000...00
SP
-127<e< 128
SP
-150<e<-126
DP
e= 1024
Fraction=
.0xx...xx
DP
e= 1024
Fraction=
.1xx...xx
DP
e= 1024
Fraction=
.000...00
DP
-127<e< 1024
DP
-127<e< 128
DP
-150<e<-126
DP
-1023<e<-149
DP
-1054<e<-1022
Note 1
The xx...xx pattern for the signaling NaNs indicates any NON-ZERO bit pattern.
MOTOROLA
INPUT DATA
signaling NaN (SNAN)
written as DP
read as SNAN (see Note 1)
non signaling NaN (QNAN)
written as DP
read as QNAN (see Note 2)
infinity in SP
written as DP
read as infinity (all formats)
normalized (all formats)
denormalized in SP
signaling NaN (SNAN)
written as DP
read as SNAN
non signaling NaN (QNAN)
written as DP
read as QNAN (see Note 2)
infinity in SP
written as DP
read as infinity (all formats)
no SP representation
normalized in DP/SEP
normalized (all formats)
denormalized in SP
normalized in DP/SEP
no SP representation
normalized in DP/SEP
denormalized (in DP/SEP)
Figure C- 1. Floating-Point Moves Summary
DSP96002 USER'S MANUAL
TAGS
U
0
SNAN
0
QNAN
0
infinity
0
1
0
SNAN
(see Notes 1,3)
0
QNAN
0
infinity
0
0
0
0
0
MOVE
MOVE
OUT
OUT
V
TYPE
RESULT
0
SP
CORRECT
DP
CORRECT
0
SP
CORRECT
DP
CORRECT
0
SP
CORRECT
DP
CORRECT
0
SP
CORRECT
DP
CORRECT
0
SP
CORRECT
DP
WRONG
0
SP
CORRECT
DP
CORRECT
0
SP
CORRECT
DP
CORRECT
0
SP
CORRECT
DP
CORRECT
0
SP
WRONG
DP
CORRECT
0
SP
TRUNC
DP
CORRECT
0
SP
WRONG
DP
CORRECT
0
SP
WRONG
DP
CORRECT
1
SP
WRONG
DP
CORRECT
D-19

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