Motorola DSP96002 User Manual page 47

4.7.16 ER Unordered Condition (UNCC) Bit 15
The unordered condition bit is set if a non-aware floating-point conditional instruction (FBcc, FJcc, FIFcc,
etc) is executed when the NaN bit is set (the unordered condition). The result of the condition tested by an
instruction depends on being able to represent the operand on the real number line. By definition, if the op-
erand is a NaN, it cannot be ordered or represented on the real number line and therefore the UNCC bit will
be set. UNCC is not affected by fixed point operations. The UNCC bit is cleared during processor reset.
4.7.17 IER IEEE Inexact Flag (SINX) Bit 16
The IEEE inexact flag is the IEEE flag for trap disabled operations that is set when the rounded result of an
operation is not exact or if it overflows without an overflow trap (i. e., the INX bit is set by the current or a
previous instruction). The SINX flag is cleared during processor reset.
4.7.18 IER IEEE Divide-by-Zero Flag (SDZ) Bit 17
The IEEE division by zero flag is the IEEE flag for trap disabled operations and is set if the dividend is a
finite nonzero number and the divisor is zero (i. e., the DZ bit is set by the current or a previous instruction).
The SDZ flag is cleared during processor reset.
4.7.19 IER IEEE Underflow Flag (SUNF) Bit 18
The IEEE underflow flag is the IEEE flag for trap disabled operations and is set when both tininess (UNF is
set) and loss of accuracy (INX is set) have been detected (i. e., the INX bit and the UNF bit were set simul-
taneously in the current or a previous instruction). The SUNF flag is cleared during processor reset.
4.7.20 IER IEEE Overflow Flag (SOVF) Bit 19
The IEEE overflow flag is the IEEE flag for trap disabled operations and is set when the destination format's
largest finite number is exceeded in magnitude by what would have been the rounded floating-point result
if the exponent range were unbounded (i. e., the OVF bit is set by the current or a previous instruction). The
SOVF flag is cleared during processor reset.
4.7.21 IER IEEE Invalid Operation Flag (SIOP) Bit 20
The IEEE invalid operation flag is the IEEE flag for trap disabled operations and is set if an operand is invalid
for the operation to be performed (i. e., the OPERR bit is set by the current or a previous instruction). The
SIOP flag is cleared during processor reset.
4.7.22 IER Rounding Mode (R0-R1) Bits 21,22
The rounding mode bits R1 and R0 specify the way in which inexact results should be rounded in floating
point operations. The rounding mode bits are cleared during processor reset.
R1 R0
0 0
0 1
1 0
1 1
4 - 8
Rounding Mode
Round to Nearest Even (default)
Round toward Zero
Round toward -Infinity
Round toward +Infinity
DSP96002 USER'S MANUAL MOTOROLA