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7.5.2 DMA Controller Programming Model
The registers comprising the DMA Controller are shown in Figure 7-25 and Figure 7-26.
31
31
30
29
28
DE
DIE
*
DTD
23
22
21
20
DCP
*
*
*
15
14
13
12
*
M6
M5
M4
7
6
5
*
*
DSS2 DSS1 DSS0 DDS2 DDS1 DDS0
Figure 7-25. DMA Controller Programming Model - Channel 0
MOTOROLA
DMA Source Modifier Register
0
DSM0
addr X:$FFFFFFDF
DMA Source Address Register
DSR0
addr X:$FFFFFFDE
DMA Source Offset Register
DSN0
addr X:$FFFFFFDD
DMA Destination Modifier Register
DDM0
addr X:$FFFFFFDB
DMA Destination Address Register
DDR0
addr X:$FFFFFFDA
DMA Destination Offset Register
DDN0
addr X:$FFFFFFD9
DMA Counter
DCO0
addr X:$FFFFFFDC
27
26
25
*
DTM1 DTM0 DMAP
19
18
17
*
*
*
11
10
9
M3
M2
M1
4
3
2
1
DSP96002 USER'S MANUAL
24
DMA Control/Status Register
DCS0
addr X:$FFFFFFD8
16
*
8
M0
0
7 - 45
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