Trap Processing; Trap (Trap) - Mitsubishi Electric M32R Series User Manual

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4.10 Trap Processing

4.10.1 Trap (TRAP)

[Occurrence Conditions]
Traps refer to software interrupts which are generated by executing the "TRAP" instruction.
Sixteen distinct traps are generated, each corresponding to one of "TRAP" instruction operands
0-15. Accordingly, sixteen vector entries are provided.
[EIT Processing]
(1) Saving SM, IE, and C bits
The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE,
and BC bits.
BSM
BIE
BC
(2) Updating SM, IE, and C bits
The SM, IE, and C bits of the PSW register are updated as shown below.
Unchanged
SM
IE
C
(3) Saving PC
When the trap instruction is executed, the "PC value of the TRAP instruction + 4" is set in
the BPC register. For example, if the "TRAP" instruction is located at address 4, the value
H'08 is set in the BPC register. Similarly, if the instruction is located at address 6, the value
H'0A is set in the BPC register. In this case, the value of the BPC register bit 30 indicates
whether the trap instruction resides on a word boundary (BPC[30] = 0) or not on a word
boundary (BPC[30] = 1).
However, in either case of the above, the address to which the "RTE" instruction returns
after completion of processing by the EIT handler is address 8. (This is because the two
low-order bits are cleared to "00" when returning to the PC.)
Normally, when the program has been written in assembler, the halfword that immediately
follows the "TRAP" instruction placed at a word boundary has the "NOP" instruction
automatically inserted by the assembler.
← SM
← IE
← C
← 0
← 0
← 0
4-20
EIT
4.10 Trap Processing
Ver.0.10