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16
16.1 Outline of the Wait Controller
The wait controller controls the number of wait cycles inserted in bus cycles during access to an
extended external area. The following outlines the wait controller.
Table 16.1.1 Outline of the Wait Controller
Item
Target space
Number of wait cycles
that can be inserted
In external extension mode and processor mode, two chip select signals (CS0, CS1) are output to
an extended external area. Two areas in it corresponding to CS0 and CS1 signals are called the
CS0 and the CS1 areas, respectively.
H'0000 0000
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
H'003F FFFF
Figure 16.1.1 CS0 and CS1 Area Address Map
Specification
Wait cycles in following memory spaces are controlled depending on operation mode
Single-chip mode
External extension mode : CS0 area (1 Mbytes), CS1 area (2 Mbytes)
Processor mode
1 to 4 wait cycles inserted by software + any number of wait cycles inserted from
____
WAIT pin (Bus cycles with 1 wait cycle are the shortest bus cycle for external
access.)
Internal ROM
area
Reserved area
CS0 area
(1 Mbytes)
CS1 area
(2 Mbytes)
<External extension mode>
16-2
16.1 Outline of the Wait Controller
: No target space (Wait controller settings have no effect)
: CS0 area (2 Mbytes), CS1 area (2 Mbytes)
___
Non-CS0 area
(Internal ROM access area)
<Processor mode>
WAIT CONTROLLER
___
___
___
CS0 area
(2 Mbytes)
CS1 area
(2 Mbytes)
Ver.0.10
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