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9
9.1 Outline of the DMAC
The 32170 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer
data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O,
and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O.
Table 9.1.1 Outline of the DMAC
Item
Number of channel
Transfer request
Maximum number
of times transferred
Transferable
address space
Transfer data size
Transfer method
Transfer mode
Direction of transfer
Channel priority
Maximum transfer rate 13.3 Mbytes per second (with 20 MHz internal peripheral clock)
Interrupt request
Transfer area
Note: Transfer operation can be cascaded between DMA channels as shown below.
Completion of one transfer in channel 0 starts DMA transfer in channel 1
Completion of one transfer in channel 1 starts DMA transfer in channel 2
Completion of one transfer in channel 2 starts DMA transfer in channel 0
Completion of one transfer in channel 3 starts DMA transfer in channel 4
Completion of one transfer in channel 5 starts DMA transfer in channel 6
Completion of one transfer in channel 6 starts DMA transfer in channel 7
Completion of one transfer in channel 7 starts DMA transfer in channel 5
Completion of one transfer in channel 8 starts DMA transfer in channel 9
Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer
in channel 5
Description
10 channels
• Software trigger
• Request from internal peripheral I/Os: A-D converter, multijunction timer, or serial
I/O (reception completed, transmit buffer empty)
• Transfer operation can be cascaded between DMA channels (Note)
256 times
• 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF)
• Transfers between internal peripheral I/Os, between internal RAM and internal
peripheral I/O, between internal RAMs are supported
16 or 8 bits
Single transfer DMA (control of the internal bus is relinquished for each transfer
performed), dual-address transfer
Single transfer mode
One of three modes can be selected for the source and destination:
• Address fixed
• Address incremental
• Ring buffered
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel
6 > channel 7 > channel 8 > channel 9 (Priority is fixed)
Group interrupt request can be generated when each transfer count register underflows.
64 Kbytes from H'0080 0000 to H'0080 FFFF
(Transferable in the entire internal RAM/SFR area)
9-2
DMAC
9.1 Outline of the DMAC
Ver.0.10
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