Mitsubishi Electric M32R Series User Manual page 575

12
(5) PTY (parity error) bit (D5)
This bit is effective in only UART mode. During CSIO mode, this bit is fixed to 0.
[Set condition]
The PTY (parity error) bit is set to 1 when the SIO Transmit/Receive Mode Register's PEN
(parity enable/disable) bit is enabled and the parity (even/odd) of the receive data does not
agree with the value that has been set by the said register's PSEL bit (parity select) bit.
[Clear condition]
The PTY bit is cleared by reading the lower byte from the SIO Receive Buffer Register or
by clearing the SIO Receive Control Register's REN (receive enable) bit. However, if an
overrun error occurs, this bit cannot be cleared by reading the lower byte from the Receive
Buffer Register. In this case, clear the REN (receive enable) bit.
(6) FLM (framing error) bit
This bit is effective in only UART mode. During CSIO mode, this bit is fixed to 0.
[Set condition]
The FLM (framing error) bit is set to 1 when the number of received bits does not agree with
one that has been selected by the SIO Transmit/Receive Mode Register.
However, if an overrun error occurs, this bit cannot be cleared by reading the lower byte
from the Receive Buffer Register. In this case, clear the REN (receive enable) bit.
[Clear condition]
The FLM bit is cleared by reading the lower byte from the SIO Receive Buffer Register or
by clearing the SIO Receive Control Register's REN (receive enable) bit
(7) ERS (Error sum) bit
[Set condition]
This flag is set to 1 when any one of overrun, framing, or parity errors is detected at
completion of reception.
[Clear condition]
If an overrun has occurred, this flag is cleared by clearing the REN (receive enable) bit.
Otherwise, this flag is cleared by reading the lower byte from the Receive Buffer Register
or clearing the SIO Receive Control Register's REN (receive enable) bit.
(D6)
(D7)
12-25
12.2 Serial I/O Related Registers
SERIAL I/O
Ver.0.10