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21
PRELIMINARY
PRELIMINARY
(6) Bus arbitration timing
Symbol
HREQ Input Setup Time before BCLK
t
su(HREQL-BCLKH)
HREQ Input Hold Time after BCLK
t
h(BCLKH-HREQL)
(7) Input transition time on JTAG pin
Symbol
Input Rising
t
r
Transition Time
Input Falling
t
f
Transition Time
Note: Stipulated values are guaranteed values when the test pin load capacitance CL=80pF.
(8) JTAG interface timing
Symbol
t
c(JTCK)
JTCK Input Cycle Time
JTCK Input High Pulse Width
t
w(JTCKH)
t
w(JTCKL)
JTCK Input Low Pulse Width
t
su(JTDI-JTCK)
JTDI, JTMS Input Setup Time
t
h(JTCK-JTDI)
JTDI, JTMS Input Hold Time
t
JTDO Output Delay Time after JTCK Fall
d(JTCK-JTDOV)
t
JTDO Output Hi-Z Delay Time after JTCK Fall
d(JTCK-JTDOX)
t
W(JTRST)
TRST Input Low Pulse Width
Note: Stipulated values are guaranteed values when the test pin load capacitance CL=80pF.
Parameter
Condition
Condition
Other than JTRST pin
(JTCK,JTDI,JTMS,JTDO)
When using
TAP
JTRST pin
When not using
TAP
Other than JTRST pin
(JTCK,JTDI,JTMS,JTDO)
When using
TAP
JTRST pin
When not using
TAP
Condition
21-14
ELECTRICAL CHARACTERISTICS
21.5 AC Characteristics
Rated Value
MIN
27
0
Rated Value
MIN
Rated Value
MIN
100
40
40
15
20
tc(JTCK)
See
Unit
Figure
21.5.9
MAX
ns
35
36
ns
See
Figure
Unit
21.5.10
MAX
ns
10
58
ns
10
2
ms
ns
10
59
ns
10
ms
2
See
Figure
Unit
21.5.11
MAX
ns
60
ns
61
ns
62
ns
63
ns
64
40
ns
65
ns
66
40
67
ns
Ver.0.10
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