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10
TOP0-5 Control Register 1 (TOP05CR1)
D8
D
Bit Name
8-11
No functions assigned
12,13
TOP5M (TOP5 operation mode selection)
14,15
TOP4M (TOP4 operation mode selection)
Note: Always make sure the counter has stopped and is idle before setting or changing operation modes.
TIN0
TIN0S
Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted.
Figure 10.3.5 Outline Diagram of TOP0-5 Clock/Enable Inputs
9
10
11
Clock bus
Input event bus
3 2 1 0
3 2 1 0
S
S
S : Selector
10-72
MULTIJUNCTION TIMERS
10.3 TOP (Output-related 16-bit Timer)
<Address:H'0080 029D>
12
13
14
TOP5M
Function
00: Single-shot output mode
01: Delayed single-shot output mode
1X: Continuous output mode
clk
TOP 0
en
clk
TOP 1
en
clk
TOP 2
en
clk
TOP 3
en
clk
TOP 4
en
clk
TOP 5
en
D15
TOP4M
<When reset:H'00>
R
W
0
–
Ver.0.10
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