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10
10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)
(1) Outline of TOP single-shot output mode
In single-shot output mode, the timer generates a pulse in width of (reload register value + 1) only
once and stops without performing any operation.
When after setting the reload register, the timer is enabled (by writing to the enable bit in software
or by external input), it loads the content of the reload register into the counter synchronously with
the count clock, letting the counter start counting. The counter counts down clock pulses and
stops when it underflows after reaching the minimum count.
The F/F output waveform in single-shot output mode is inverted (F/F output levels change from
low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse
waveform in width of (reload register set value + 1) only once. Also, an interrupt can be generated
when the counter underflows.
The count value is (reload register set value + 1). In the case shown below, for example, if the
reload register value = 7, then the count value = 8.
Because all internal circuits operate synchronously with the count clock, a finite time equal to a
prescaler delay is included before F/F output changes state after the timer is enabled.
Count clock
Counter
Reload
register
F/F output
Interrupt
Note 1: What you actually see in the cycle immediately after reload is
Note 2: This diagram does not show detail timing information.
Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode
1
2
Enable
(Note 1)
(7)
6
7
* A finite time equal to a prescaler delay is
included before F/F output changes state
after the timer is enabled.
the previous counter value, and not 7.
10.3 TOP (Output-related 16-bit Timer)
Count value =8
3
4
5
6
5
4
3
2
10-84
MULTIJUNCTION TIMERS
7
8
1
0
H'FFFF
Underflow
Ver.0.10
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