Mitsubishi Electric M32R Series User Manual page 9

8.4 Port Peripheral Circuits .................................................................................. 8-31
CHAPTER 9 DMAC
9.1 Outline of the DMAC ......................................................................................... 9-2
9.2 DMAC Related Registers .................................................................................. 9-4
9.2.1 DMA Channel Control Register .................................................................. 9-6
9.2.2 DMA Software Request Generation Registers ......................................... 9-17
9.2.3 DMA Source Address Registers ............................................................... 9-18
9.2.4 DMA Destination Address Registers ........................................................ 9-19
9.2.5 DMA Transfer Count Registers ................................................................. 9-20
9.2.6 DMA Interrupt Request Status Registers .................................................. 9-21
9.2.7 DMA Interrupt Mask Registers .................................................................. 9-23
9.3 Functional Description of the DMAC ............................................................ 9-27
9.3.1 Cause of DMA Request ............................................................................ 9-27
9.3.2 DMA Transfer Processing Procedure ....................................................... 9-31
9.3.3 Starting DMA ............................................................................................ 9-32
9.3.4 Channel Priority ........................................................................................ 9-32
9.3.5 Gaining and Releasing Control of the Internal Bus ................................... 9-32
9.3.6 Transfer Units ........................................................................................... 9-33
9.3.7 Transfer Counts ........................................................................................ 9-33
9.3.8 Address Space ......................................................................................... 9-33
9.3.9 Transfer Operation .................................................................................... 9-33
9.3.10 End of DMA and Interrupt ....................................................................... 9-37
9.3.11 Status of Each Register after Completion of DMA Transfer ................... 9-37
9.4 Precautions about the DMAC ........................................................................ 9-38
CHAPTER 10 MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers ................................................................... 10-2
10.2 Common Units of Multijunction Timer ........................................................ 10-9
10.2.1 Timer Common Register Map ................................................................. 10-9
10.2.2 Prescaler Unit ....................................................................................... 10-12
10.2.3 Clock Bus/Input-Output Event Bus Control Unit ................................... 10-13
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