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10
TOP0-10 Count Enable Register (TOPCEN)
D0
1
2
D
Bit Name
0-4
No functions assigned
5
TOP10CEN (TOP10 count enable)
6
TOP9CEN (TOP9 count enable)
7
TOP8CEN (TOP8 count enable)
8
TOP7CEN (TOP7 count enable)
9
TOP6CEN (TOP6 count enable)
10
TOP5CEN (TOP5 count enable)
11
TOP4CEN (TOP4 count enable)
12
TOP3CEN (TOP3 count enable)
13
TOP2CEN (TOP2 count enable)
14
TOP1CEN (TOP1 count enable)
15
TOP0CEN (TOP0 count enable)
Note: This register must always be accessed in halfwords.
The TOP0-10 Count Enable Register controls the operation of TOP counter. To enable the counter
in software, enable the relevant TOP0-10 Enable Protect Register for write and set the count
enable bit by writing a 1. To stop the counter, enable the TOP0-10 Enable Protect Register for write
and reset the count enable bit by writing a 0.
In all but continuous mode, when the counter stops due to an occurrence of underflow, the count
enable bit is automatically reset to 0. Therefore, what you get by reading the TOP0-10 Count
Enable Register is the status that indicates the counter's operating status (active or idle).
3
4
5
6
TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0
CEN
CEN
CEN
10-82
MULTIJUNCTION TIMERS
10.3 TOP (Output-related 16-bit Timer)
7
8
9
10
11
CEN
CEN
CEN
CEN
Function
0: Stops count
1: Enables count
<Address:H'0080 02FE>
12
13
14
D15
CEN
CEN
CEN
CEN
<When reset:H'0000>
R
0
Ver.0.10
W
–
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