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9
Software start
One DMA2 transfer completed
A-D conversion completed
MJT (input event bus 2)
MJT (output event bus 0)
MJT (TIN13 input signal)
One DMA0 transfer completed
MJT (output event bus 1)
MJT (TIN18 input signal)
One DMA1 transfer completed
Serial I/O0 (transmit buffer empty)
Serial I/O1 (reception completed)
MJT (TIN0 input signal)
One DMA3 transfer completed
Serial I/O0 (reception completed)
MJT (TIN19 input signal)
Software start
One DMA7 transfer completed
All DMA0 transfers completed (udf)
Serial I/O2 (reception completed)
MJT (TIN20 input signal)
Serial I/O1 (transmit buffer empty)
MJT (TIN1 input signal)
One DMA5 transfer completed
Serial I/O2 (transmit buffer empty)
MJT (TIN2 input signal)
One DMA6 transfer completed
MJT (input event bus 0)
Serial I/O3 (reception completed)
MJT (TIN7 input signal)
Serial I/O3 (transmit buffer empty)
MJT (TIN8 input signal)
One DMA8 transfer completed
Figure 9.1.1 Block Diagram of the DMAC
DMA channel 0
DMA
request
MJT (TIO8_udf)
selector
DMA channel 1
Software start
DMA
request
selector
DMA channel 2
Software start
DMA
request
selector
DMA channel 3
Software start
DMA
request
selector
DMA channel 4
Software start
DMA
request
selector
DMA channel 5
DMA
request
selector
DMA channel 6
Software start
DMA
request
selector
DMA channel 7
Software start
DMA
request
selector
DMA channel 8
Software start
DMA
request
selector
DMA channel 9
Software start
DMA
request
selector
9-3
9.1 Outline of the DMAC
Source address
register
Destination address
register
Transfer count
udf
register
Source
Destination
udf
Transfer count
Source
Destination
udf
Transfer count
Source
Destination
Transfer count
udf
Source
Destination
Transfer count
udf
DMA start
Determination block
Internal bus arbitration
Source
Destination
Transfer count
udf
Source
Destination
udf
Transfer count
Source
Destination
udf
Transfer count
Source
Destination
Transfer count
udf
Source
Destination
Transfer count
udf
DMA start
Determination block
Internal bus arbitration
DMAC
Interrupt
request
Interrupt
request
Ver.0.10
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