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21
PRELIMINARY
PRELIMINARY
Address
(A11-A30)
CS0, CS1
RD
WR
BLE , BHE
Data output
(D0-D15)
Note 1: Stipulated values are guaranteed values when the test pin load capacitance CL =
15 to 50 pF.
Note 2: Input and output signals are determined high or low with respect to TTL level.
Figure 21.5.8 Write Timing (Byte enable mode)
BCLK
tsu(HREQL-BCLKH)
35
HREQ
0.16VCCE
HACK
Figure 21.5.9 Bus Arbitration Timing
0.43VCCE
0.16VCCE
td(RDH-BLEL)
80
td(RDH-BHEL)
0.43VCCE
td(CS-WRL)
70
td(A-WRL)
69
0.16VCCE
td(BLEL-WRL)
73
td(BHEL-WRL)
0.16VCCE
td(WRL-D)
75
0.43VCCE
0.16VCCE
0.16VCCE
36
th(BCLKH-HREQL)
37
td(BCLKL-HACKL)
21-22
ELECTRICAL CHARACTERISTICS
0.43VCCE
0.16VCCE
tv(WRH-CS)
72
71
tv(WRH-A)
68
tw(WRL)
0.43VCCE
0.16VCCE
tv(WRH-BLEL)
74
tv(WRH-BHEL)
0.16VCCE
tpxz(WRH-DZ)
77
tv(WRH-D)
76
0.43VCCE
0.16VCCE
0.16VCCE
21.5 AC Characteristics
td(BLEH-RDL)
81
td(BHEH-RDL)
0.16VCCE
0.43VCCE
tv(BCLKL-HACKL)
38
0.16VCCE
Ver.0.10
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