10
Clock bus
TIN2
TIN2S
Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted.
Figure 10.3.7 Outline Diagram of TOP8-10 Clock/Enable Inputs
Input event bus
3 2 1 0
3 2 1 0
S
S
: Selector
S
10-76
MULTIJUNCTION TIMERS
10.3 TOP (Output-related 16-bit Timer)
clk
TOP 8
en
clk
TOP 9
en
clk
TOP 10
en
Ver.0.10