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12
12.3.5 Processing at End of CSIO Transmission
When data transmission is completed, the following operation is automatically performed in
hardware.
(1) When not transmitting successively
• The transmit status bit is set to 0.
(2) When transmitting successively
• When transmission of the last data in a consecutive data train is completed, the transmit status
bit is set to 0.
12.3.6 Transmit Interrupt
If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit
buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to
the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN
(transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt
has been enabled.
You must set the Interrupt Controller (ICU) before you can use transmit interrupts.
12.3.7 Transmit DMA Transfer Request
When data has been transferred from the transmit buffer register to the transmit shift register, a
transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This
transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being
disabled).
You must set the Interrupt Controller (ICU) before you can transmit data using DMA transfers.
12.3 Transmit Operation in CSIO Mode
12-32
SERIAL I/O
Ver.0.10
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