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1
Clock
Port 7
Reset
Mode
CAN
Port 22
Port 19
Port 17
Port 15
Port 14
Port 13
Multi-
junction
Port 12
timer
Port 21
Port 18
Port 16
Port 11
Port 10
Port 9
A-D
Port 6
converter
Port 6
Port 22
Interrupt
Port 6
controller
DBGUG
Note1.
Note2.
Note3.
Figure 1.3.2 Pin Function Diagram of 255FBGA
XIN
XOUT
VCNT
OSC-VCC
OSC-VSS
P70/BCLK/WR
RESET
MOD0
MOD1
FP
P220/CTX
P221/CRX
34
P190
P197/TIN26
TIN33
–
–
P172, P173/TIN24, TIN25
P150
P157/TIN0
TIN7
–
–
P140
P147/TIN8
TIN15
–
–
P130
P137/TIN16
TIN23
–
–
4
P124
P127/
–
TCLK0
TCLK 3
–
45
P210
P217/TO37
TO44
–
–
P180
–
P187/TO29
–
TO36
P160
P167/TO21
TO28
–
–
P110
P117/TO0
TO7
–
–
P100
P107/TO8
TO15
–
–
P93
P97/TO16
TO20
–
–
16
AD0IN0
AD0IN15
–
16
AD1IN0
AD1IN15
–
P67/ADTRG
2
AVCC0, AVCC1
2
AVSS0, AVSS1
2
AVREF0, AVREF1
3
P61
P63
–
P222, P223
P64/SBI
TRCLK
TRSYNC
TRDATA
8
JDBI
JEVENTO
JEVENT1
7
VCCE
6
VCCI
:
denotes blocks operating with a 3.3 V power supply
3.3V
:
denotes blocks operating with a 5 V power supply.
5V
Use caution when using this port because it has a debug event function.
255FBGA is currently under development.
1-11
P45/CS1
P44/CS0
P43/RD
P42/BHW/BHE
P41/BLW/BLE
P71/WAIT
P72/HREQ
P73/HACK
P224/A11 (Note2)
P225/A12 (Note2)
20
P20
P27/A23
A30
–
–
P30
P37/A15
A22
–
–
P46, P47/A13, A14
16
P00
P07/DB0
DB7
–
–
P10
P17/DB8
DB15
–
–
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
P200/TXD4
P201/RXD4
P202/TXD5
P203/RXD5
P65/SCLKI4/SCLKO4
P66/SCLKI5/SCLKO5
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
JTMS
JTCK
JTRST
JTDO
JTDI
VDD
FVCC
16
VSS
OVERVIEW
1.3 Pin Function
Port 4
Bus
control
Port 7
Port 22
Port 2
Address
Port 3
bus
Port 4
Port 0
Data
bus
Port 1
Port 6
Port 8
Serial
Port17
I/O
Port 20
Real-time
Port 7
debugger
JTAG
Ver.0.10
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