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7 DETAILS OF INSTRUCTIONS
ld.a %rd, %pc
Function
24-bit data transfer
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
1
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Src: Register direct %pc
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
The content of the PC (PC + 2) is transferred to the rd register.
Example
ld.a
%r0,%pc
Caution
• When this instruction is executed, a value equal to the PC of this instruction plus 2 is loaded into
the register. This instruction must be executed as a delayed slot instruction. If it does not follow
a delayed branch instruction, the PC value that is loaded into the rd register may not be the next
instruction address to the ld.a instruction.
• This instruction must be used as a delayed slot instruction for jr*.d, jpr.d or jpa.d.
7-64
rd(23:0) ← pc(23:0) + 2
9
8
7
6
|
|
1
1
1
r d
0
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
; r0 ← pc + 2
Seiko Epson Corporation
5
4
3
2
1
0
1
1
0
0
0
0
|
|
|
|
|
|
S1C17 CORE MANUAL
(REV. 1.2)
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