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7 DETAILS OF INSTRUCTIONS
jpr
%rb
jpr.d %rb
Function
Unconditional PC relative jump
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
0
|
|
0
0
0
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Signed PC relative
CLK
jpr
jpr.d
Description
(1) Standard
jpr
The content of the rb register is added to the PC (PC + 2), and the program branches to that
address. The LSB of the rb register is ignored and is always handled as 0.
(2) Delayed branch (d bit (bit 7) = 1)
jpr.d
For the jpr.d instruction, the next instruction becomes a delayed slot instruction. A delayed
slot instruction is executed before the program branches. Interrupts are masked in intervals
between the jpr.d instruction and the next instruction, so no interrupts occur.
Example
jpr
%r0
Caution
When the jpr.d instruction (delayed branch) is used, be careful to ensure that the next instruction
is limited to those that can be used as a delayed slot instruction. If any other instruction is executed,
the program may operate indeterminately. For the usable instructions, refer to the instruction list in
the Appendix.
7-40
pc ← pc + 2 + rb
9
8
7
6
|
0
0
0
0
1
0
1
|
|
|
|
|
|
|
0
0
0
0
1
1
1
|
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
Three cycles
Two cycles (when a one-cycle delayed slot instruction follows), Three cycles (other)
%rb
%rb
; pc ← pc + 2 + r0
Seiko Epson Corporation
5
4
3
2
1
0
|
0
0
0
r b
|
|
|
|
|
|
0
0
0
r b
|
|
|
|
|
jpr
jpr.d
S1C17 CORE MANUAL
(REV. 1.2)
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