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5 INSTRUCTION SET
5.5 Logical Operation Instructions
Four discrete logical operation instructions are available for use with the S1C17 Core.
Logical AND
and
Logical OR
or
Exclusive-OR
xor
Logical NOT
not
All logical operations are performed in a specified general-purpose register (R0–R7). The source is one of two, ei-
ther 16-bit data in a specified general-purpose register or immediate data (7, 13, or 16 bits).
When a logical operation is performed, the V flag (bit 2) in the PSR is cleared.
Conditional execution
The logical operation instructions for between registers (op %rd,%rs) allow use of the switches to specify
whether the instruction will be executed or not depending on the C flag status.
Unconditional execution instructions
op
%rd,%rs
The instruction without a switch will be always executed regardless how the C flag is set.
Example: and
%rd,%rs
Instructions executable under C condition
op/c
%rd,%rs
The instruction with the /c switch will be executed only when the C flag has been set to 1.
Example: or/c
Instructions executable under NC condition
op/nc
%rd,%rs
The instruction with the /nc switch will be executed only when the C flag has been cleared to 0.
Example: xor/nc
5-14
(op = and, or, xor, not)
(op = and, or, xor, not)
%rd,%rs
(op = and, or, xor, not)
%rd,%rs
Seiko Epson Corporation
S1C17 CORE MANUAL
(REV. 1.2)
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