Epson S1C17 Series Manual page 131

7 DETAILS OF INSTRUCTIONS
(2) Standard (example of post-increment option)
ld.a
The 32-bit data (the eight high-order bits are ignored) in the specified memory location is
transferred to the rd register. The SP contains the memory address to be accessed. The memory
address will be incremented by four bytes after the data transfer has finished.
(3) Extension 1 (example of post-decrement option)
ext
ld.a
The 32-bit data (the eight high-order bits are ignored) in the specified memory location is
transferred to the rd register. The SP contains the memory address to be accessed. The memory
address will be decremented by imm13 bytes after the data transfer has finished.
(4) Extension 2 (example of pre-decrement option)
ext
ext
ld
After the memory address specified by the SP is decremented by imm24 bytes, the 32-bit data (the
eight high-order bits are ignored) in the decremented address is transferred to the rd register.
(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Caution
The immediate must specify a 32-bit boundary address (two least significant bits = 0). Specifying
other address causes an address misaligned interrupt. Note, however, that the data transfer is
performed by setting the two least significant bits of the address to 0.
7-72
%rd,[%sp]+ ; source memory address = sp
; post increment: sp + 4
imm13
%rd,[%sp]- ; source memory address = sp
; post decrement: sp - imm13
imm11 ; imm11(10:0) = imm24(23:13)
imm13 ; = imm24(12:0)
%rd,-[%sp] ; source memory address = sp - imm24
Seiko Epson Corporation
S1C17 CORE MANUAL
(REV. 1.2)