Table of Contents
Advertisement
Coprocessor Interface Instructions
Mnemonic
Opcode
Operand
MSB
ld.cw
%rd, %rs
0
0
1
1
0
%rd, imm7
0
1
1
1
1
ld.ca
%rd, %rs
0
0
1
1
0
%rd, imm7
0
1
1
1
1
ld.cf
%rd, %rs
0
0
1
1
0
%rd, imm7
1
1
0
1
0
Remarks
*1) With one EXT: co_dout1 output = imm20, With two EXT: co_dout1 output = imm24
Code
LSB
1
rd
0
0
1
0
rs
co_dout0←rd, co_dout1←rs
0
rd
imm7
co_dout0←rd, co_dout1←imm7
1
rd
0
0
1
1
rs
co_dout0←rd, co_dout1←rs, rd←co_din, psr(C, V, Z, N)←co_cvzn
1
rd
imm7
co_dout0←rd, co_dout1←imm7, rd←co_din, psr(C, V, Z, N)←co_cvzn
1
rd
0
0
0
1
rs
co_dout0←rd, co_dout1←rs, psr(C, V, Z, N)←co_cvzn
1
rd
imm7
co_dout0←rd, co_dout1←imm7, psr(C, V, Z, N)←co_cvzn
Function
S1C17 Core Instruction Set
Flags
Cycle
EXT
D
IL
IE
C
V
Z
N
1
–
–
–
–
–
–
–
1
–
–
–
–
–
–
*1
1
–
–
↔
↔
↔
↔
–
1
–
–
↔
↔
↔
↔
*1
↔
↔
↔
↔
1
–
–
–
↔
↔
↔
↔
*1
1
–
–
Advertisement
Table of Contents
