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(2) Standard (example of post-increment option)
ld
[%rb]+,%rs
The 16 low-order bits of the rs register are transferred to the specified memory location. The rb
register contains the memory address to be accessed. The memory address will be incremented
by two bytes after the data transfer has finished.
(3) Extension 1 (example of post-decrement option)
ext
ld
The 16 low-order bits of the rs register are transferred to the specified memory location. The rb
register contains the memory address to be accessed. The memory address will be decremented
by imm13 bytes after the data transfer has finished.
(4) Extension 2 (example of pre-decrement option)
ext
ext
ld
-[%rb],%rs
After the memory address specified by the rb register is decremented by imm24 bytes, the 16
low-order bits of the rs register are transferred to the decremented address.
(5) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Caution
The rb register and the immediate value must specify a 16-bit boundary address (least significant
bit = 0). Specifying an odd address causes an address misaligned interrupt. Note, however, that the
data transfer is performed by setting the least significant bit of the address to 0.
S1C17 CORE MANUAL
(Rev. 1.2)
; Destination memory address = rb
; post increment: rb + 2
imm13
[%rb]-,%rs
; Destination memory address = rb
; post decrement: rb - imm13
imm11
; imm11(10:0) = imm24(23:13)
imm13
; = imm24(12:0)
; Destination memory address = rb - imm24
Seiko Epson Corporation
7 DETAILS OF INSTRUCTIONS
7-61
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