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7 DETAILS OF INSTRUCTIONS
ld %rd, [%sp + imm7]
Function
16-bit data transfer
Standard)
Extension 1) rd(15:0) ← W[sp + imm20], rd(23:16) ← 0
Extension 2) rd(15:0) ← W[sp + imm24], rd(23:16) ← 0
15 14 13 12 11 10
Code
1
1
1
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Src: Register indirect with displacement
Dst: Register direct %rd = %r0 to %r7
CLK
Two cycles
Description
(1) Standard
ld
%rd,[%sp + imm7]
The 16-bit data in the specified memory location is transferred to the rd register. The content
of the current SP with the 7-bit immediate imm7 added as displacement comprises the memory
address to be accessed. The eight high-order bits of the rd register are set to 0.
(2) Extension 1
ext
ld
The ext instruction extends the displacement to a 20-bit quantity. As a result, the content of the
SP with the 20-bit immediate imm20 added comprises the memory address, the 16-bit data in
which is transferred to the rd register. The eight high-order bits of the rd register are set to 0.
(3) Extension 2
ext
ext
ld
The two ext instructions extend the displacement to a 24-bit quantity. As a result, the content
of the SP with the 24-bit immediate imm24 added comprises the memory address, the 16-bit
data in which is transferred to the rd register. The eight high-order bits of the rd register are set
to 0.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext
0x1
ld
%r0,[%sp + 0x2]
Caution
The SP and the displacement must specify a 16-bit boundary address (least significant bit = 0).
Specifying an odd address causes an address misaligned interrupt. Note, however, that the data
transfer is performed by setting the least significant bit of the address to 0.
7-56
rd(15:0) ← W[sp + imm7], rd(23:16) ← 0
9
8
7
6
|
|
0
1
0
r d
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
imm13
%rd,[%sp + imm7]
imm4
imm13
%rd,[%sp + imm7]
; r0 ← [sp + 0x82]
Seiko Epson Corporation
5
4
3
2
1
0
imm7
|
|
|
|
|
|
; memory address = sp + imm7
; = imm20(19:7)
; memory address = sp + imm20,
; imm7 = imm20(6:0)
; imm4(3:0) = imm24(23:20)
; = imm24(19:7)
; memory address = sp + imm24,
; imm7 = imm24(6:0)
S1C17 CORE MANUAL
(REV. 1.2)
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