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7 DETAILS OF INSTRUCTIONS
ld %rd, %rs
16-bit data transfer
Function
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
1
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
The 16 low-order bits of the rs register are transferred to the rd register. The eight high-order
bits of the rd register are set to 0.
(2) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit.
Example
ld
%r0,%r1
7-52
rd(15:0) ← rs(15:0), rd(23:16) ← 0
9
8
7
6
|
|
0
1
0
0
r d
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
; r0 ← r1(15:0)
Seiko Epson Corporation
5
4
3
2
1
0
|
0
1
0
r s
|
|
|
|
|
S1C17 CORE MANUAL
(REV. 1.2)
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