Ld.a %Rd, [Imm7] - Epson S1C17 Series Manual

7 DETAILS OF INSTRUCTIONS

ld.a %rd, [imm7]

Function 32-bit data transfer
Standard)
Extension 1) rd(23:0) ← A[imm20](23:0), ignored ← A[imm20](31:24)
Extension 2) rd(23:0) ← A[imm24](23:0), ignored ← A[imm24](31:24)
15 14 13 12 11 10
Code
1 1 0
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IL IE C
Flag
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– – –
Mode Src: Immediate data (unsigned)
Dst: Register direct %rd = %r0 to %r7
CLK One cycle
Description (1) Standard
ld.a
The 32-bit data (the eight high-order bits are ignored) in the memory address specified with the
7-bit immediate imm7 is transferred to the rd register.
(2) Extension 1
ext
ld.a
The ext instruction extends the displacement to a 20-bit quantity. As a result, the 32-bit data (the
eight high-order bits are ignored) in the memory address specified with the 20-bit immediate
imm20 is transferred to the rd register.
(3) Extension 2
ext
ext
ld.a
The two ext instructions extend the displacement to a 24-bit quantity. As a result, the 32-bit
data (the eight high-order bits are ignored) in the memory address specified with the 24-bit
immediate imm24 is transferred to the rd register.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext 0x1
%r0,[0x4] ; r0 ← [0x84]
ld.a
Caution
The imm7 must specify a 32-bit boundary address (two least significant bits = 0). Specifying other
address causes an address misaligned interrupt. Note, however, that the data transfer is performed
by setting the two least significant bits of the address to 0.
7-74
rd(23:0) ← A[imm7](23:0), ignored ← A[imm7](31:24)
9 8 7 6
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0 1 1 r d
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V Z N
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– – –
%rd,[imm7] ; memory address = imm7
imm13 ; = imm20(19:7)
%rd,[imm7] ; memory address = imm20, imm7 = imm20(6:0)
imm4 ; imm4(3:0) = imm24(23:20)
imm13 ; = imm24(19:7)
%rd,[imm7] ; memory address = imm24, imm7 = imm24(6:0)
Seiko Epson Corporation
5 4 3 2 1 0
imm7
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S1C17 CORE MANUAL
(REV. 1.2)