Sub.a %Sp, %Rs - Epson S1C17 Series Manual

7 DETAILS OF INSTRUCTIONS

sub.a %sp, %rs

Function 24-bit subtraction
Standard)
Extension 1) sp(23:0) ← rs(23:0) - imm13(zero extended)
Extension 2) sp(23:0) ← rs(23:0) - imm24
15 14 13 12 11 10
Code
0 0 1
| |
IL IE C
Flag
| |
– – –
Mode Src: Register direct %rs = %r0 to %r7
Dst: Register direct %sp
CLK One cycle
Description (1) Standard
sub.a
The content of the rs register is subtracted from the stack pointer SP.
(2) Extension 1
ext
sub.a
The 13-bit immediate imm13 is subtracted from the content of the rs register after being zero-
extended, and the result is loaded into the stack pointer SP. The content of the rs register is not
altered.
(3) Extension 2
ext
ext
sub.a
The 24-bit immediate imm24 is subtracted from the content of the rs register, and the result is
loaded into the stack pointer SP. The content of the rs register is not altered.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example (1) sub.a
(2) ext
ext
sub.a
Caution The 2 low-order bits of the subtruction results are always loaded to the SP as 0.
7-130
sp(23:0) ← sp(23:0) - rs(23:0)
9 8 7 6
1 0 0 0 0 0 0
| | | | | | |
V Z N
| | |
– – –
; sp ← sp - rs
%sp,%rs
imm13
; sp ← rs - imm13
%sp,%rs
imm11 ; imm11(10:0) = imm24(23:13)
imm13 ; = imm24(12:0)
; sp ← rs - imm24
%sp,%rs
%sp,%r0 ; sp = sp - r0
0x1
0x1ffc
%sp,%r2 ; sp = r2 - 0x3ffc
Seiko Epson Corporation
5 4 3 2 1 0
|
0 1 1 r s
| | | | |
S1C17 CORE MANUAL
(REV. 1.2)