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7 DETAILS OF INSTRUCTIONS
and %rd, sign7
Function
16-bit logical AND
Standard)
Extension 1) rd(15:0) ← rd(15:0) & sign16, rd(23:16) ← 0
Extension 2) Unusable
15 14 13 12 11 10
Code
1
0
1
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IL
IE
C
Flag
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–
–
–
Mode
Src: Immediate data (signed)
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
and
The content of the rd register and the sign-extended 7-bit immediate sign7 are logically AND'
ed, and the result is loaded into the rd register. The operation is performed in 16-bit size, and
bits 23–16 of the rd register are set to 0.
(2) Extension 1
ext
and
The content of the rd register and the 16-bit immediate sign16 are logically AND'ed, and the
result is loaded into the rd register. The operation is performed in 16-bit size, and bits 23–16 of
the rd register are set to 0.
(3) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
(1) and
(2) ext
and
7-12
rd(15:0) ← rd(15:0) & sign7(sign extended), rd(23:16) ← 0
9
8
7
6
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0
0
0
r d
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V
Z
N
|
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0 ↔ ↔
; rd ← rd & sign7
%rd,sign7
imm9
; imm9(8:0) = sign16(15:7)
; rd ← rd & sign16, sign7 = sign16(6:0)
%rd,sign7
%r0,0x7e
; r0 = r0 & 0xfffe
0x3f
%r1,0x7f
; r1 = r1 & 0x1fff
Seiko Epson Corporation
5
4
3
2
1
0
sign7
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S1C17 CORE MANUAL
(REV. 1.2)
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