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6 FUNCTIONS
6.5.3 Registers for Debugging
The reserved core I/O area contains the debug registers described below.
0xFFFF90: Debug RAM Base Register (DBRAM)
Register name
Address
Bit
Debug RAM
FFFF90
D31–24
base register
(L)
D23
|
D0
D[23:0]
DBRAM[23:0]: Debug RAM Base Address Bits
This is a read-only register that contains the start address of a work area (64 bytes) for debugging.
0xFFFFA0: Debug Control Register (DCR)
Register name
Address
Bit
Debug control
FFFFA0
D7–5
register
(B)
D4
D3
D2
D1
D0
D[7:5]
Reserved
D4
DR: Debug Request Flag
Indicates whether an external debug request has occurred or not.
1 (R):
Occurred
0 (R):
Not occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
This flag is cleared (reset to 0) by writing 1. The flag must be cleared before the debug handler routine
has been terminated by executing the retd instruction.
D3
IBE1: Instruction Break #1 Enable Bit
Enables/disables instruction break #1.
1 (R/W): Enable
0 (R/W): Disable (default)
When this bit is set to 1, instruction fetch addresses will be compared with the value set in the
Instruction Break Address Register 1 (0xffffb4), and an instruction break will occur if they are matched.
Setting this bit to 0 disables the comparison.
D2
IBE0: Instruction Break #0 Enable Bit
Enables/disables instruction break #0.
1 (R/W): Enable
0 (R/W): Disable (default)
When this bit is set to 1, instruction fetch addresses will be compared with the value set in the
Instruction Break Address Register 0 (0xffffb0), and an instruction break will occur if they are matched.
Setting this bit to 0 disables the comparison.
D1
SE: Single Step Enable Bit
Enables/disables single-step execution.
1 (R/W): Enable
0 (R/W): Disable (default)
D0
DM: Debug Mode Bit
Indicates the current operation mode of the processor (debug mode or user mode).
1 (R):
Debug mode
0 (R):
User mode (default)
6-12
Name
Function
–
Unused (fixed at 0)
DBRAM23
Debug RAM base address
|
DBRAM[5:0] is fixed at 0x0.
DBRAM0
Name
Function
–
Reserved
DR
Debug request flag
IBE1
Instruction break #1 enable
IBE0
Instruction break #0 enable
SE
Single step enable
DM
Debug mode
Seiko Epson Corporation
Setting
Init. R/W
0x0
0x0
*
0x0–0xFFFDC0
(64 byte units)
Setting
Init. R/W
–
–
1 Occurred
0 Not occurred
0
1 Enable
0 Disable
0
1 Enable
0 Disable
0
1 Enable
0 Disable
0
1 Debug mode 0 User mode
0
Remarks
R
R
Initial value is set in
the C17 RTL-define
DBRAM_BASE.
Remarks
–
0 when being read.
R/W
Reset by writing 1.
R/W
R/W
R/W
R
S1C17 CORE MANUAL
(REV. 1.2)
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