Table of Contents
Advertisement
6 FUNCTIONS
6.2 Program Execution
Following initial reset, the processor loads the reset vector (address of the reset handler routine) into the PC and
starts executing instructions beginning with the address. As the instructions in the S1C17 Core are fixed to 16 bits
in length, the PC is incremented by 2 each time an instruction is fetched from the address indicated by the PC. In
this way, instructions are executed successively.
When a branch instruction is executed, the processor checks the PSR flags and whether the branch conditions have
been satisfied, and loads the jump address into the PC.
When an interrupt occurs, the processor loads the address for the interrupt handler routine from the vector table into
the PC.
The vector table contains interrupt vectors beginning with the reset vector and is located from the address set in the
TTBR register (0xffff80). The start address can be set to the TTBR in the configuration.
6.2.1 Instruction Fetch and Execution
Internally in the S1C17 Core, instructions are processed in three pipelined stages, so that the basic instructions
except for the branch instructions and data transfer instructions with the memory address increment/decrement
function can be executed in one clock cycle.
Pipelining speeds up instruction processing by executing one instruction while fetching another. In the 3-stage
pipeline, each instruction is processed in three stages, with processing of instructions occurring in parallel, for
faster instruction execution.
Basic instruction stages
Instruction fetch
Instruction decode
Hereinafter, each stage is represented by the following symbols:
F (for Fetch):
Instruction fetch
D (for Decode): Instruction decode
E (for Execute): Instruction execution, memory access, register write
Pipelined operation
PC + 2
PC + 4
Note: The pipelined operation shown above uses the internal memory. If external memory or low-speed
external devices are used, one or more wait cycles may be inserted depending on the devices
used, with the E stage kept waiting.
6-2
Instruction execution / Memory access / Register write
Clock
F
D
PC
F
Figure 6.2.1.1 Pipelined Operation
Seiko Epson Corporation
E
D
E
F
D
E
S1C17 CORE MANUAL
(REV. 1.2)
Advertisement
Table of Contents
