Epson S1C17 Series Manual page 51

Cmos 16-bit single chip microcontroller
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Classification
Shift and swap
sr
sa
sl
swap
Immediate extension
ext
Conversion
cv.ab
cv.as
cv.al
cv.la
cv.ls
Branch
jpr
jpr.d
jpa
ipa.d
jrgt
jrgt.d
jrge
jrge.d
jrlt
jrlt.d
jrle
jrle.d
jrugt
jrugt.d
jruge
jruge.d
jrult
jrult.d
jrule
jrule.d
jreq
jreq.d
jrne
jrne.d
call
call.d
calla
calla.d
ret
ret.d
int
intl
reti
reti.d
brk
retd
System control
nop
halt
slp
ei
di
Coprocessor control
ld.cw
ld.ca
ld.cf
S1C17 CORE MANUAL
(Rev. 1.2)
Mnemonic
Cycle
1
%rd,%rs
1
%rd,imm7
1
%rd,%rs
1
%rd,imm7
1
%rd,%rs
1
%rd,imm7
1
%rd,%rs
1
imm13
1
%rd,%rs
1
%rd,%rs
1
%rd,%rs
1
%rd,%rs
1
%rd,%rs
3
sign10
*3
2(.d)
%rb
3
imm7
*3
2(.d)
%rb
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
*2
2–3
sign7
*3
2(.d)
4
sign10
*3
3(.d)
%rb
4
imm7
*3
3(.d)
%rb
3
*3
2(.d)
3
imm5
3
imm5,imm3
3
*3
2(.d)
4
4
1
6
6
1
1
1
%rd,%rs
%rd,imm7
1
%rd,%rs
%rd,imm7
1
%rd,%rs
%rd,imm7
Seiko Epson Corporation
Flag
IL
IE
C
V
Z
0
0
0
1
0
6 FUNCTIONS
Remark
N
*2: 2 cycles when not
jumped
3 cycles when jumped
*3: When a 1-cycle delayed
slot instruction follows
Same values as one
without (.d) when a 2-
cycle delayed slot
instruction follows
6-5

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