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ld [imm7], %rs
Function
16-bit data transfer
Standard)
Extension 1) W[imm20] ← rs(15:0)
Extension 2) W[imm24] ← rs(15:0)
15 14 13 12 11 10
Code
1
1
0
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Immediate data (unsigned)
CLK
One cycle
Description
(1) Standard
ld
[imm7],%rs
The 16 low-order bits of the rs register are transferred to the memory address specified with the
7-bit immediate imm7.
(2) Extension 1
ext
ld
The ext instruction extends the memory address to a 20-bit quantity. As a result, the 16 low-
order bits of the rs register are transferred to the memory address specified with the 20-bit
immediate imm20.
(3) Extension 2
ext
ext
ld
The two ext instructions extend the memory address to a 24-bit quantity. As a result, the 16
low-order bits of the rs register are transferred to the memory address specified with the 24-bit
immediate imm24.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the "d" bit. In this case, extension of the immediate by the ext
instruction cannot be performed.
Example
ext
0x1
ld
[0x2],%r0
Caution
The imm7 must specify a 16-bit boundary address (least significant bit = 0). Specifying an odd
address causes an address misaligned interrupt. Note, however, that the data transfer is performed
by setting the least significant bit of the address to 0.
S1C17 CORE MANUAL
(Rev. 1.2)
W[imm7] ← rs(15:0)
9
8
7
6
|
|
1
1
0
r s
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
; memory address = imm7
imm13
; = imm20(19:7)
[imm7],%rs
; memory address = imm20, imm7 = imm20(6:0)
imm4
; imm4(3:0) = imm24(23:20)
imm13
; = imm24(19:7)
[imm7],%rs
; memory address = imm24, imm7 = imm24(6:0)
; W[0x82] ← 16 low-order bits of r0
Seiko Epson Corporation
5
4
3
2
1
0
imm7
|
|
|
|
|
|
7 DETAILS OF INSTRUCTIONS
7-63
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