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6.5 Debug Circuit
The S1C17 Core has a debug circuit to assist in software development by the user.
6.5.1 Debugging Functions
The debug circuit provides the following functions:
• Instruction break
A debug interrupt is generated before the set instruction address is executed. An instruction break can be set at
two addresses.
• Single step
A debug interrupt is generated every instruction executed.
• Forcible break
A debug interrupt is generated by an external input signal.
• Software break
A debug interrupt is generated when the brk instruction is executed.
When a debug interrupt occurs, the processor performs the following processing:
(1) Suspends the instructions currently being executed.
(2) Saves the contents of the PC and PSR, and R0, in that order, to the addresses specified below.
PC/PSR → DBRAM + 0x0
→ DBRAM + 0x4
R0
(3) Loads address 0xfffc00 to PC and branches to the debug interrupt handler routine.
In the interrupt handler routine, the retd instruction should be executed at the end of processing to return to the
suspended instructions. When returning from the interrupt by the retd instruction, the processor restores the saved
data in order of the R0 and the PC and PSR.
Neither hardware interrupts nor NMI interrupts are accepted during a debug interrupt.
6.5.2 Resource Requirements and Debugging Tools
The on-chip debug function requires a 64-byte work area. For the work area for debugging, refer to the Technical
Manual of each model.
Debugging is performed by connecting a serial ICE to the debug pins of the S1C17 Core and entering debug
commands from the debugger being run on a personal computer. The tools listed below are required for debugging.
• S1C17 Family Serial ICE (S5U1C17001H)
• S1C17 Family C Compiler Package
S1C17 CORE MANUAL
(Rev. 1.2)
(DBRAM: Start address of the work area for debugging in the user RAM)
Seiko Epson Corporation
6 FUNCTIONS
6-11
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