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Branch Instructions
Mnemonic
Opcode
Operand
MSB
jpr / jpr.d
sign10
0
0
0
1
%rb
0
0
0
0
jpa / jpa.d
imm7
0
0
0
0
%rb
0
0
0
0
jrgt / jrgt.d
sign7
0
0
0
0
jrge / jrge.d
sign7
0
0
0
0
jrlt / jrlt.d
sign7
0
0
0
0
jrle / jrle.d
sign7
0
0
0
0
jrugt / jrugt.d
sign7
0
0
0
0
jruge / jruge.d
sign7
0
0
0
0
jrult / jrult.d
sign7
0
0
0
0
jrule / jrule.d
sign7
0
0
0
0
jreq / jreq.d
sign7
0
0
0
0
jrne / jrne.d
sign7
0
0
0
0
call / call.d
sign10
0
0
0
1
%rb
0
0
0
0
calla / calla.d
imm7
0
0
0
0
%rb
0
0
0
0
ret / ret.d
0
0
0
0
int
imm5
0
1
1
1
intl
imm5, imm3
0
1
1
1
reti / reti.d
0
0
0
0
brk
0
0
0
0
retd
0
0
0
0
Remarks
*1) With one EXT: displacement = sign21 (= {imm13, sign7, 0}), With two EXT: displacement = sign24 (= {1st imm13(2:0), 2nd imm13, sign7, 0})
*2) With one EXT: absolute address= sign20 (= {imm13, imm7}), With two EXT: absolute address = sign24 (= {1st imm13(3:0), 2nd imm13, imm7})
*3) These instructions become a delayed branch instruction when the d bit in the code is set to 1 by suffixing ".d" to the opcode (jrgt.d, call.d, etc.).
*4) With one EXT: displacement = sign24 (= {imm13, sign10, 0})
*5) The conditional branch instructions other than delayed slot instructions (without ".d") are executed in two cycles when the program flow does not branch or three cycles when the program flow branches.
*6) The value with (.d) attached shows the number of cycles when 1-cycle delayed slot instruction follows. Otherwise, the same number of cycles as that shown without (.d) is required.
Immediate Extension Instruction
Mnemonic
Opcode
Operand
MSB
ext
imm13
0 1 0
Remarks
*1) One or two ext instruction can be placed prior to the instructions that can be extended.
Code
LSB
0
d
sign10
pc←pc+2+sign11; sign11={sign10,0} (*3)
0
0
0
1
d
1
0
0
0
rb
pc←pc+2+rb (*3)
0
0
1
1
d
imm7
pc←imm7 (*3)
0
0
0
1
d
1
0
0
1
rb
pc←rb (*3)
0
1
1
0
d
sign7
pc←pc+2+sign8 if !Z&!(N^V) is true; sign8={sign7,0} (*3)
0
1
1
1
d
sign7
pc←pc+2+sign8 if !(N^V) is true; sign8={sign7,0} (*3)
1
0
0
0
d
sign7
pc←pc+2+sign8 if N^V is true; sign8={sign7,0} (*3)
1
0
0
1
d
sign7
pc←pc+2+sign8 if Z | (N^V) is true; sign8={sign7,0} (*3)
1
0
1
0
d
sign7
pc←pc+2+sign8 if !Z&!C is true; sign8={sign7,0} (*3)
1
0
1
1
d
sign7
pc←pc+2+sign8 if !C is true; sign8={sign7,0} (*3)
1
1
0
0
d
sign7
pc←pc+2+sign8 if C is true; sign8={sign7,0} (*3)
1
1
0
1
d
sign7
pc←pc+2+sign8 if Z | C is true; sign8={sign7,0} (*3)
1
1
1
0
d
sign7
pc←pc+2+sign8 if Z is true; sign8={sign7,0} (*3)
1
1
1
1
d
sign7
pc←pc+2+sign8 if !Z is true; sign8={sign7,0} (*3)
1
d
sign10
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+sign11; sign11={sign10,0} (*3)
0
0
0
1
d
0
0
0
0
rb
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+rb (*3)
0
1
0
1
d
imm7
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←imm7 (*3)
0
0
0
1
d
0
0
0
1
rb
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←rb (*3)
0
0
0
1
d
0
1
0
0
0
0
0
pc←A[sp](23:0), sp←sp+4 (*3)
0
1
0
0
0
imm5
0
1
sp←sp-4, A[sp]←{psr, pc+2}, pc←vector(TTBR+imm5×4)
0
1
imm3
imm5
1
1
sp←sp-4, A[sp]←{psr, pc+2}, pc←vector(TTBR+imm5×4), psr(IL)←imm3
0
0
0
1
d
0
1
0
1
0
0
0
{psr, pc}←A[sp], sp←sp+4
0
0
0
1
0
1
1
0
0
0
0
0
A[DBRAM]←{psr, pc+2}, A[DBRAM+4]←r0, pc←0xfffc00
0
0
0
1
0
1
1
0
1
0
0
0
r0←A[DBRAM+4](23:0), {psr, pc}←A[DBRAM]
Code
LSB
imm13
Extends the immediate or operand of the following instruction.
Function
Function
S1C17 Core Instruction Set
Flags
Cycle
EXT
D
*6
IL
IE
C
V
Z
N
–
–
–
–
–
–
*4
–
3
–
–
–
–
–
–
–
–
2(.d)
–
–
–
–
–
–
*2
–
3
–
–
–
–
–
–
–
–
*1
2(.d)
–
–
–
–
–
–
–
*1
–
–
–
–
–
–
–
*1
2
–
–
–
–
–
–
–
*1
(false)
–
–
–
–
–
–
–
*1
or
–
–
–
–
–
–
–
*1
3
–
–
–
–
–
–
–
*1
(true)
–
–
–
–
–
–
–
*5
*1
–
–
–
–
–
–
–
*1
–
–
–
–
–
–
–
*1
2(.d)
–
–
–
–
–
–
–
*4
–
–
–
–
–
–
–
4
–
–
–
–
–
–
–
–
*2
3(.d)
–
–
–
–
–
–
–
4
–
–
–
–
–
–
–
–
3(.d)
–
–
–
–
–
–
–
–
3, 2(.d)
–
0
–
–
–
–
–
–
3
↔
0
–
–
–
–
–
–
3
↔
↔
↔
↔
↔
↔
–
–
3, 2(.d)
–
0
–
–
–
–
–
–
4
↔
↔
↔
↔
↔
↔
–
–
S1C17 Core Instruction Set
Flags
Cycle
EXT
D
IL
IE
C
V
Z
N
*1
1
–
–
–
–
–
–
–
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