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Data Transfer Instructions (1)
Mnemonic
Opcode
Operand
MSB
ld.b
%rd, %rs
0
0
1
0
%rd, [%rb]
0
0
1
0
%rd, [%rb]+
0
0
1
0
%rd, [%rb]-
0
0
1
0
%rd, -[%rb]
0
0
1
0
%rd, [%sp+imm7]
1
1
1
0
%rd, [imm7]
1
1
0
0
[%rb], %rs
0
0
1
0
[%rb]+, %rs
0
0
1
0
[%rb]-, %rs
0
0
1
0
-[%rb], %rs
0
0
1
0
[%sp+imm7], %rs
1
1
1
1
[imm7], %rs
1
1
0
1
ld.ub
%rd, %rs
0
0
1
0
0
0
1
0
%rd, [%rb]
%rd, [%rb]+
0
0
1
0
%rd, [%rb]-
0
0
1
0
%rd, -[%rb]
0
0
1
0
%rd, [%sp+imm7]
1
1
1
0
%rd, [imm7]
1
1
0
0
ld
%rd, %rs
0
0
1
0
%rd, sign7
1
0
0
1
%rd, [%rb]
0
0
1
0
%rd, [%rb]+
0
0
1
0
%rd, [%rb]-
0
0
1
0
%rd, -[%rb]
0
0
1
0
%rd, [%sp+imm7]
1
1
1
0
%rd, [imm7]
1
1
0
0
[%rb], %rs
0
0
1
0
[%rb]+, %rs
0
0
1
0
[%rb]-, %rs
0
0
1
0
-[%rb], %rs
0
0
1
0
Remarks
*1) With one EXT: base address = rb+imm13, With two EXT: base address = rb+imm24
*2) With one EXT: data = sign16
*3) With one EXT: data = imm20, With two EXT: data = imm24
*4) With one EXT: base address = imm20, With two EXT: base address = imm24
*5) With one EXT: base address = sp+imm20, With two EXT: base address = sp+imm24
*6) With one EXT: base address = rb, address increment/decrement rb/sp ← rb/sp±imm13, With two EXT: base address = rb, address increment/decrement rb/sp ← rb/sp±imm24
*7) With no EXT: 1 cycle, With EXT: 2 cycles
Code
LSB
1
0
rd
0
0
0
0
rs
rd(7:0)←rs(7:0), rd(15:8)←rs(7), rd(23:16)←0
0
0
rd
0
0
0
0
rb
rd(7:0)←B[rb], rd(15:8)←B[rb](7), rd(23:16)←0
0
0
rd
0
1
0
0
rb
rd(7:0)←B[rb], rd(15:8)←B[rb](7), rd(23:16)←0, rb(23:0)←rb(23:0)+1
0
0
rd
1
1
0
0
rb
rd(7:0)←B[rb], rd(15:8)←B[rb](7), rd(23:16)←0, rb(23:0)←rb(23:0)-1
0
0
rd
1
0
0
0
rb
rb(23:0)←rb(23:0)-1, rd(7:0)←B[rb], rd(15:8)←B[rb](7), rd(23:16)←0
0
0
rd
imm7
rd(7:0)←B[sp+imm7], rd(15:8)←B[sp+imm7](7), rd(23:16)←0
0
0
rd
imm7
rd(7:0)←B[imm7], rd(15:8)←B[imm7](7), rd(23:16)←0
0
1
rs
0
0
0
0
rb
B[rb]←rs(7:0)
0
1
rs
0
1
0
0
rb
B[rb]←rs(7:0), rb(23:0)←rb(23:0)+1
0
1
rs
1
1
0
0
rb
B[rb]←rs(7:0), rb(23:0)←rb(23:0)-1
0
1
rs
1
0
0
0
rb
rb(23:0)←rb(23:0)-1, B[rb]←rs(7:0)
0
0
rs
imm7
B[sp+imm7]←rs(7:0)
0
0
rs
imm7
B[imm7]←rs(7:0)
1
0
rd
0
0
0
1
rs
rd(7:0)←rs(7:0), rd(15:8)←0, rd(23:16)←0
0
0
rd
0
0
0
1
rb
rd(7:0)←B[rb], rd(15:8)←0, rd(23:16)←0
0
0
rd
0
1
0
1
rb
rd(7:0)←B[rb], rd(15:8)←0, rd(23:16)←0, rb(23:0)←rb(23:0)+1
0
0
rd
1
1
0
1
rb
rd(7:0)←B[rb], rd(15:8)←0, rd(23:16)←0, rb(23:0)←rb(23:0)-1
0
0
rd
1
0
0
1
rb
rb(23:0)←rb(23:0)-1, rd(7:0)←B[rb], rd(15:8)←0, rd(23:16)←0
0
1
rd
imm7
rd(7:0)←B[sp+imm7], rd(15:8)←0, rd(23:16)←0
0
1
rd
imm7
rd(7:0)←B[imm7], rd(15:8)←0, rd(23:16)←0
1
0
rd
0
0
1
0
rs
rd(15:0)←rs(15:0), rd(23:16)←0
1
0
rd
sign7
rd(6:0)←sign7(6:0), rd(15:7)←sign7(6), rd(23:16)←0
0
0
rd
0
0
1
0
rb
rd(15:0)←W[rb], rd(23:16)←0
0
0
rd
0
1
1
0
rb
rd(15:0)←W[rb], rd(23:16)←0, rb(23:0)←rb(23:0)+2
0
0
rd
1
1
1
0
rb
rd(15:0)←W[rb], rd(23:16)←0, rb(23:0)←rb(23:0)-2
0
0
rd
1
0
1
0
rb
rb(23:0)←rb(23:0)-2, rd(15:0)←W[rb], rd(23:16)←0
1
0
rd
imm7
rd(15:0)←W[sp+imm7], rd(23:16)←0
1
0
rd
imm7
rd(15:0)←W[imm7], rd(23:16)←0
rs
rb
0
1
0
0
1
0
W[rb]←rs(15:0)
0
1
rs
0
1
1
0
rb
W[rb]←rs(15:0), rb(23:0)←rb(23:0)+2
0
1
rs
1
1
1
0
rb
W[rb]←rs(15:0), rb(23:0)←rb(23:0)-2
0
1
rs
1
0
1
0
rb
rb(23:0)←rb(23:0)-2, W[rb]←rs(15:0)
Function
S1C17 Core Instruction Set
Flags
Cycle
EXT
D
IL
IE
C
V
Z
N
1
–
–
–
–
–
–
–
1, 2
*7
–
–
–
–
–
–
*1
*6
2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
2
–
–
–
–
–
–
*5
*4
1
–
–
–
–
–
–
*7
*1
1, 2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
2
–
–
–
–
–
–
*6
*5
2
–
–
–
–
–
–
*4
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
1, 2
*7
*1
–
–
–
–
–
–
2
–
–
–
–
–
–
*6
*6
2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
*5
2
–
–
–
–
–
–
1
–
–
–
–
–
–
*4
1
–
–
–
–
–
–
–
*2
1
–
–
–
–
–
–
*7
*1
1, 2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
2
–
–
–
–
–
–
*6
*6
2
–
–
–
–
–
–
*5
2
–
–
–
–
–
–
*4
1
–
–
–
–
–
–
1, 2
*7
*1
–
–
–
–
–
–
2
–
–
–
–
–
–
*6
*6
2
–
–
–
–
–
–
*6
2
–
–
–
–
–
–
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