Motorola CPU32 Reference Manual page 10

Paragraph
Number
7.2.7.2
7.2.8
7.2.8.1
7.2.8.2
7.2.8.3
7.2.8.4
7.2.8.5
7.2.8.6
7.2.8.7
7.2.8.8
7.2.8.9
7.2.8.10
7.2.8.11
7.2.8.12
7.2.8.13
7.2.8.14
7.2.8.15
7.2.8.16
7.3
7.3.1
7.3.2
7.3.3
8.1
8.1.1
8.1.2
8.1.3
8.1.3.1
8.1.3.2
8.1.3.3
8.1.4
8.1.5
8.1.6
8.1.7
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
TABLE OF CONTENTS (Continued)
Title
Page
Number
Development System Serial Logic ................................................ .7-12
Command Set ......................................................................................... 7-14
Command Format .............................................................................. 7-14
Command Sequence Diagrams ..................................................... 7-15
Command Set Summary .................................................................. 7-17
Read NO Register (RAREG/ROREG) ............................................. 7-19
Write NO Register (WAREG/wDREG) ........................................... 7-19
Read System Register (RSREG) ..................................................... 7-20
Write System Register (WSREG) .................................................... 7-21
Read Memory Location (READ) ...................................................... 7-22
Write Memory Location (WRITE) .................................................... .7-23
Dump Memory Block (DUMP) ......................................................... 7-25
Fill Memory Block (FILL) ................................................................... 7-26
Resume Execution (GO) ................................................................... 7-27
Call User Code (CALL) ..................................................................... 7-28
Reset Peripherals (RST) ................................................................... 7-30
No Operation (NOP) .......................................................................... 7-31
Future Commands ............................................................................. 7-31
Deterministic Opcode Tracking ................................................................ 7-32
Instruction Fetch (IFETCH) .................................................................... 7-32
Instruction Pipe (IPIPE) .......................................................................... 7 -32
Opcode Tracking during Loop Mode .................................................. 7-34
Section 8
Instruction Execution Timing
Resource Scheduling ................................................................................ 8-1
Microsequencer ...................................................................................... 8-1
Instruction Pipeline ................................................................................. 8-2
Bus Controller Resources ..................................................................... 8-3
Prefetch Controller ............................................................................. 8-3
Write-Pending Buffer ......................................................................... 8-3
Microbus Controller ........................................................................... 8-4
Instruction Execution Overlap .............................................................. 8-4
Effects of Wait States ............................................................................. 8-5
Instruction Execution Time Calculation .............................................. 8-6
Effects of Negative Tails ........................................................................ 8-7
Instruction Stream Timing Examples ...................................................... 8-8
Timing Example 1: Execution Overlap ............................................... 8-8
Timing Example 2: Branch Instructions .............................................. 8-9
Timing Example 3: Negative Tails ....................................................... 8-10
Instruction Timing Tables .......................................................................... 8-11
Fetch Effective Address ......................................................................... 8-13
Calculate Effective Address .................................................................. 8-15
CPU32 REFERENCE MANUAL MOTOROLA
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