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7.2.7.1 CPU Serial Logic
CPU serial logic, shown in the left-hand portion of Figure 7-5, consists of
transmit and receive shift registers and of control logic that includes
synchronization, serial clock generation circuitry, and a received bit counter.
CPU
DEVELOPMENT SYSTEM
INSTRUCTION
REGISTER BUS
DATA
~6
0
{16
I
RCVDATALATCH
I
I
COMMAND LATCH
I
,
~
SERIAL IN
'"'.
DSI
PARALLEL IN
-
PARALLEL OUT
~
'~
SERIAL OUT
DSO
l
W
PARALLEL IN
SERIAL IN
SERIAL OUT
~
~
PARALLEL OUT
U
16
~
STATUS~
RESULT LATCH
EXECUTION ,,\
STlus
f6
UNIT
SYNCHRONIZE
DATA
MICROSEQUENCER
tt I
I
CONTROL
I
DSCLK
I
CONTROL
SERIAL
LOGIC
j
I
LOGIC
CLOCK
Figure 7-5. Debug Serial
1/0
Block Diagram
MOTOROLA
7-10
DEVELOPMENT
SUPPORT
CPU32 REFERENCE MANUAL
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