Motorola CPU32 Reference Manual page 339

Section 8.3.1 Fetch Effective Address gives addressing mode data. For
(d8, An, Xn.Sz
*
Scale), head
=
4, tail
=
2, cycles
=
8 (2/1/0). Because this
example is for a long access and the FEA table lists data for word accesses,
add two clocks to the tail and to the number of cycles ("X" table notation), to
obtain head
=
4, tail
=
4, cycles
=
10(2/1/0)
Assuming that no trailing write exists from the previous instruction, effective
address calculation requires six clocks. Replacement fetch for the effective
address occurs during these six clocks, leaving a head of four. If there is no
time in the head to perform a prefetch, due to a previous trailing write, then
additional time to do the prefetches must be allotted in the middle of the
instruction or after the tail.
10 2 1 0
roTAL NUM,m OF
CLOC~ r r 1
NUMBER OF READ CYCLES
NUMBER OF INSTRUCTION ACCESS CYCLES
NUMBER OF WRITE CYCLE8-------l
The total number of bus-activity clocks is:
(2 Reads x 2 Clocks/Read)
+
(1 Instruction Access x 2 Clocks/Access)
+
(0 Writes x 2 ClockslWrite)
=
6 Clocks of Bus Activity
The number of internal clocks (not overlapped by bus activity) is:
10 Clocks Total- 6 Clocks Bus Activity
=
4 Internal Clocks
Memory read requires two bus cycles at two clocks each. This read time,
implied in the tail figure for the effective address, cannot be overlapped with the
instruction because the instruction has a head of zero.
An additional two clocks are required for the ADD instruction itself.
The total is 6
+
4
+
2 = 12 clocks. If bus cycles take more time (Le., the memory
is off-chip), add an appropriate number of clocks to each memory access.
The instruction sequence MOVE.L DO, (AO) followed by LSL.L #7, D2 provides
an example of overlapped execution. The MOVE instruction has a head of zero
and a tail of four, because it is a long write. The LSL instruction has a head of
four. The trailing write from the MOVE overlaps the LSL head completely.
Thus, the two-instruction sequence has a head of zero and a tail of zero, and a
total execution of eight rather than 12 clocks.
MOTOROLA
8-12
INSTRUCTION EXECUTION CPU32 REFERENCE MANUAL
TIMING