Motorola CPU32 Reference Manual page 277

A trace exception can be viewed as an extension to the function of any
instruction. If a trace exception is generated by an instruction, the execution of
that instruction is not complete until the trace exception processing associated
with it is also complete:
If an instruction is aborted by a bus error or address error exception, trace
exception processing is deferred until the suspended instruction is restarted
and completed normally. An RTE from a bus error or address error will not
be traced because of the possibility of continuing the instruction from the
fault.
If an instruction is executed and an interrupt is pending on completion, the
trace exception is processed before the interrupt exception.
If an instruction forces an exception, the forced exception is processed
before the trace exception.
If an instruction is executed and a breakpoint is pending upon completion of
the instruction, the trace exception is processed before the breakpoint.
If an attempt is made to execute an illegal, unimplemented, or privileged
instruction while tracing is enabled, no trace exception will occur because
the instruction is not executed. This is particularly important to an emulation
routine that performs an instruction function, adjusts the stacked program
counter to beyond the unimplemented instruction, and then returns. The
status register on the stack must be checked to determine if tracing is on
before the return is executed. If tracing is on, trace exception processing
must be emulated so that the trace exception handler can account for the
emulated instruction.
Tracing also affects normal operation of the STOP and LPSTOP instructions. If
either begins execution with T1 set, a trace exception will be taken after the
instruction loads the status register. Upon return from the trace handler routine,
execution will continue with the instruction following STOP (LPSTOP), and the
processor will not enter the stopped condition.
6.2.11 Interrupts
There are seven levels of interrupt priority and 192 assignable interrupt vectors
within each exception vector table. Judicious use of multiple vector tables and
hardware chaining will permit a virtually unlimited number of peripherals to
interrupt the processor.
MOTOROLA
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EXCEPTION PROCESSING CPU32 REFERENCE MANUAL