Table of Contents
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CPU,
Serial Logic, 7-10
Space,5-4ff
- 0 -
Data,
BDM Serial Format, 7-11
Movement Instructions, 4-8
Register Direct Addressing Mode, 3-4
Registers, 2-4
Structures, Other (Stacks and Queues), 3-19
Types, 2-4
Deterministic Opcode Tracking, 7-2, 7-32
Development Features, Standard, 7-1
Development Support, 7-1
Development System Serial Logic, 7-12
Double Bus Faults, 7-5, 6-8
Dynamic Bus Sizing, 6-19, 6-29
- E -
Effective Address, 3-4
Calculation Timing Table (CEA), 8-13
Encoding Summary, 3-12
Fetch Timing Table (FEA), 8-12
Enhanced Addressing Modes, 1-4
Enhanced Instruction Set, 1-5
Errors, Bus, 6-8
Exception,
Address Error, 6-9
Breakpoint Instruction (BKPT), 6-10
Bus Error, 6-8
Definition of Exception Processing, 6-1
Format Error, 6-11
Illegal Instruction, 6-11
Instruction Traps, 6-9
Interrupts, 6-14
Multiple, 6-4
Priority, 6-5
Privilege Violation, 6-12
Processing Sequence, 6-3
Reset, 6-6
Related Instructions and Operations, 8-24
Return from, 6-16
Stack Frame, 6-4
Trace, 6-13
Types, 6-3
Unimplemented Instruction, 6-11
Vectors, 6-1
Execution Time Calculations, 8-6ff
Execution Overlap, 8-8
MOTOROLA
2
INDEX
- F -
Faults,
Correcting, 6-22
Type I via Software, 6-23
Type I via RTE, 6-23
Type II via RTE, 6-24
Type III via Software, 6-24
Type III via Conversion and Restart, 6-25
Type
III
via RTE, 6-25
Type IV via Software, 6-25
Recovery, 6-17
Types of, 6-20
Type I, Released Write, 6-20
Type II, Prefetch, Operand, RMW, MOVEP, 6-20
Type III, MOVEM Operand Transfer, 6-21
Type IV, Exception Processing, 6-22
Fetch Effective Address, Timing Table, 8-12
Format Error, 6-11
Four-Word Stack Frame, Normal, 6-26
Function Code Registers, 2-4, 2-6
Future BDM Commands, 7-31
-G-
General Description, 1-1
-H
Halt Operation, 5-1
- 1 -
Illegal or Unimplemented Instruction, 6-11
Immediate,
Arithmetic/Logic Instruction Timing, 8-20
Data Addressing, 3-11
Implicit Reference, 3-3
Indexed Addressing, 3-6, 3-9
Indirect Addressing, 3-5ff
CPU32 REFERENCE MANUAL
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Table of Contents
