Motorola CPU32 Reference Manual page 281

III
0 - Operand or prefetch bus fault
1 - Exception processing bus fault
MV is set when the operand transfer portion of the MOVEM instruction is in
progress at the time of a bus fault. If a prefetch bus fault occurs while refetching
the MOVEM opcode and extension word, both the MVand IN bits will be set.
o -
MOVEM was not in progress when fault occurred
1 - MOVEM in progress when fault occurred
TR indicates that a trace exception was pending when a bus error exception
was processed. The instruction that generated the trace will not be restarted
upon return from the exception handler. This includes MOVEM and released
write bus errors indicated by the assertion of either MV or RR in the SSW.
0 - Trace not pending
1 - Trace pending
B1 indicates that a breakpoint exception was pending on channel 1 (external
breakpoint source) when a bus error exception was processed. Pending
breakpoint status is stacked, regardless of the type of bus error exception.
o -
Breakpoint not pending
1 - Breakpoint pending
BO indicates that a breakpoint exception was pending on channel 0 (internal
breakpoint source) when the bus error exception was processed. Pending
breakpoint status is stacked, regardless of the type of bus error exception.
o -
Breakpoint not pending
1 - Breakpoint pending
RR will be set if the faulted bus cycle was a released write. If the write is
completed (rerun) in the exception handler, the RR bit should be cleared before
executing RTE. The bus cycle will be rerun if the RR bit is set upon return from
the exception handler.
o -
Faulted cycle was read, RMW, or unreleased write
1 - Faulted cycle was a released write
Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking.
0-
Faulted cycle was non-RMW cycle
1 - Faulted cycle was either the read or write of an RMW cycle
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EXCEPTION PROCESSING CPU32 REFERENCE MANUAL