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8.3.5 Arithmetic/Logic Instructions
The arithmetic/logic instruction table indicates the number of clock periods
needed to perform the specified arithmetic/logical instruction using the specified
addressing mode.
Footnotes indicate when to account for the appropriate
effective address times.
The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total
clock cycle number. All timing data assumes two-clock reads and writes.
MOTOROLA
8-18
Instruction
Head
Tail
Cycles
ADD(A)
Rn,Rm
0
0
2(0/1/0)
ADD(A)
(FE A), Rn
0
0
2(0/1/0)
ADD
Dn, (FEA)
0
3
5(0/1/x)
AND
Dn,Dm
0
0
2(0/1/0)
AND
(FEA), Dn
0
0
2(0/1/0)
AND
Dn, (FEA)
0
3
5(0/1/x)
EOR
Dn,Dm
0
0
2(0/1/0)
EOR
Dn, (FEA)
0
3
5(0/1/x)
OR
Dn,Dm
0
0
2(0/1/0)
OR
(FEA), Dn
0
0
2(0/1/0)
OR
Dn, (FEA)
0
3
5(0/1/x)
SUB(A)
Rn,Rm
0
0
2(0/1/0)
SUB(A)
(FEA), Rn
0
0
2(0/1/0)
SUB
Dn, (FEA)
0
3
5(0/1/x)
CMP(A)
Rn,Rm
0
0
2(0/1/0)
CMP(A)
(FEA), Rn
0
0
2(0/1/0)
CMP2 (Save)*
(FEA), Rn
1
1
3(0/1/0)
CMP2 (Op)
(FEA), Rn
2
0
16-18(x/1/0)
MUL(S/U).W
(FEA), Dn
0
0
26(0/1/0)
MUL(S/U).L (Save)*
(FEA), Dn
1
1
3(0/1/0)
MUL(S/U).L (Op)
(FEA), DI
2
0
46 - 52(0/1/0)
MUL(S/U).L (Op)
(FEA), Dn:DI
2
0
46(0/1/0)
DIVU.W
(FEA), Dn
0
0
32(0/1/0)
DIVS.W
(FEA), Dn
0
0
42(0/1/0)
DIVU.L (Save)*
(FEA), Dn
1
1
3(0/1/0)
DIVU.L (Op)
(FEA), Dn
2
0
<46(0/1/0)
DIVS.L (Save)*
(FEA). Dn
1
1
3(0/1/0)
DIVS.L (Op)
(FEA), Dn
2
0
<62(0/1/0)
TBL(S/U)
Dn:Dm. Dp
26
0
28-30(0/2/0)
INSTRUCTION EXECUTION
CPU32 REFERENCE MANUAL
TIMING
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