Motorola CPU32 Reference Manual page 157

III
MOVEM
Move Multiple Registers
Operation:
Assembler
Syntax:
Attributes:
Registers ==> Destination
Source ==> Registers
MOVEM register list, (ea)
MOVEM (ea), register list
Size
=
(Word, Long)
MOVEM
Description: Moves the contents of selected registers to or from consecutive memory locations
starting at the location specified by the effective address. A register is selected if the bit in the
mask field corresponding to that register is set. The instruction size determines whether 16 or 32
bits of each register are transferred. In the case of a word transfer to either address or data
registers, each word is sign-extended to 32 bits, and the resulting long word is loaded into the
associated register.
Selecting the addressing mode also selects the mode of operation of the MOVEM instruction,
and only the control modes, the predecrement mode, and the postincrement mode are valid. If
the effective address is specified by one of the control modes, the registers are transferred
starting at the specified address, and the address is incremented by the operand length (2 or 4)
following each transfer. The order of the registers is from data register 0 to data register 7, then
from address register 0 to address register 7.
If the effective address is specified by the predecrement mode, only a register-to-memory
operation is allowed. The registers are stored starting at the specified address minus the operand
length (2 or 4), and the address is decremented by the operand length following each transfer.
The order of storing is from address register 7 to address register 0, then from data register 7 to
data register O. When the instruction has completed, the decremented address register contains
the address of the last operand stored. In the CPU 32, if the addressing register is also moved to
memory, the value written is the decremented value.
If the effective address is specified by the postincrement mode, only a memory-to-register
operation is allowed. The registers are loaded starting at the specified address; the address is
incremented by the operand length (2 or 4) following each transfer. The order of loading is the
same as that of control mode addressing. When the instruction has completed, the incremented
address register contains the address of the last operand loaded plus the operand length. In the
CPU32, if the addressing register is also loaded from memory, the value loaded is the value
fetched plus the operand length.
MOTOROLA
4-104
INSTRUCTION SET CPU32 REFERENCE MANUAL