Motorola CPU32 Reference Manual page 271

6.2.2 Bus Error
A bus error exception occurs when an assertion of the BERR signal is
acknowledged. The BERR signal can be asserted by one of three sources:
1. External logic by assertion of the BERR input pin
2. Direct assertion of the internal BERR signal by an internal module
3. Direct assertion of the internal BERR signal by the on-chip hardware
watchdog after detecting a no-response condition
Bus error exception processing begins when the processor attempts to use
information from an aborted bus cycle.
When the aborted bus cycle is an instruction prefetch, the processor will not
initiate exception processing unless the prefetched information is used. For
example, if a branch instruction flushes an aborted prefetch, that word is not
accessed, and no exception occurs.
When the aborted bus cycle is a data access, the processor initiates exception
processing immediately, except in the case of released operand writes.
Released write bus errors are delayed until the next instruction boundary or
until another operand access is attempted.
Exception processing for bus error exceptions follows the regular sequence, but
context preservation is more involved than for other exceptions because a bus
exception can be initiated while an instruction is executing. Several bus error
stack format organizations are utilized to provide additional information
regarding the nature of the fault.
First, any register altered by a faulted-instruction effective address calculation is
restored to its initial value. Then a special status word (SSW) is placed on the
stack. The SSW contains specific Information about the aborted access - size,
type of access (read or write), bus cycle type, and function code are saved.
Finally, fault address, bus error exception vector number, program counter
value, and a copy of the status register are saved.
If a bus error occurs during exception processing for a bus error, an address
error, a reset, or while the processor is loading stack information during RTE
execution, the processor halts. This simplifies isolation of catastrophic system
failure by preventing processor interaction with stacks and memory. Only
assertion of RESET can restart a halted processor.
MOTOROLA
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EXCEPTION PROCESSING CPU32 REFERENCE MANUAL