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DATA
BUS
R
B
EXTENSION
WORDS
R
C
OPCODES
RESIDUAL
Figure 7-11. Functional Model of Instruction Pipeline
Assertion of IPIPE for a single clock cycle indicates the use of data from IRS.
Regardless of the presence of valid data in IRA, the contents of IRS are
invalidated when IPIPE is asserted.
If IRA contains valid data, the data is
copied into IRS (IRA
~
IRS), and the IRS stage is revalidated.
Assertion of IPIPE for two clock cycles indicates the start of a new instruction
and subsequent replacement of data in IRe. This action causes a full advance
of the pipeline (IRS
~
IRe and IRA
~
IRS). IRA is refilled during the next
instruction fetch bus cycle.
Data loaded into IRA propagates automatically through subsequent empty
pipeline stages. Signals that show the progress of instructions through IRS and
IRe are necessary to accurately monitor pipeline operation. These signals are
provided by IRA and IRS validity bits. When a pipeline advance occurs, the
validity bit of the stage being loaded is set and the validity bit of the stage
supplying the data is negated.
Secause instruction execution is not timed to bus activity, IPIPE is synchronized
II
with the system clock and not the bus. Figure 7-12 illustrates the timing in
relation to the system clock.
CPU32 REFERENCE MANUAL
DEVELOPMENT SUPPORT
MOTOROLA
7-33
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