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LPSTOP
Low Power Stop
Operation:
Assembler
Syntax:
Attributes:
If supervisor state
then Immediate Data
~
SR
Interrupt Mask
~
External Bus Interface (EBI)
STOP
else TRAP
LPSTOP #(data)
Size
=
(Word) Privileged
LPSTOP
Description:
The immediate operand is moved into the entire status register, the program counter is
advanced to point to the next instruction, and the processor stops fetching and executing
instructions. A CPU LPSTOP broadcast cycle is executed to CPU space $3 to copy the updated
interrupt mask to the external bus interface (EBI). The internal clocks are stopped.
Execution of instructions resumes when a trace, interrupt, or reset exception occurs. A trace
exception occurs if the trace state is on when the LPSTOP instruction is executed. If an interrupt
request is asserted with a higher priority that the current priority level set by the new status register
value, an interrupt exception occurs; otherwise the interrupt request is ignored. If the bit of the
immediate data corresponding to the S bit is off, execution of the instruction causes a privilege
violation. An external reset always initiates reset exception processing.
Condition Codes:
Set according to the immediate operand.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
o
IMMEDIATE DATA
Instruction Fields:
Immediate field:
Specifies the data to be loaded into the status register.
MOTOROLA
4-90
INSTRUCTION SET
5
4
3
2
o
o
o
CPU32 REFERENCE MANUAL
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