Motorola CPU32 Reference Manual page 276

6.2.10 Tracing
To aid in program development, M68000 processors include a facility to allow
tracing of instruction execution. CPU32 tracing also has the ability to trap on
changes in program flow. In trace mode, a trace exception is generated after
each instruction executes, allowing a debugging program to monitor the
execution of a program under test. The T1 and TO bits in the supervisor portion
of the status register are used to control tracing.
When T[1 :0] = 00, tracing is disabled, and instruction execution proceeds
normally (see Table 6-3).
Table 6-3. Tracing Control
T1 TO
Tracing Function
0 0
No
tracing
0
1
Trace on change of flow
1 0 Trace on instruction execution
1 1 (Undefined; reserved)
When T[1 :0]
=
01 at the beginning of instruction execution, a trace exception will
be generated if the program counter changes sequence during execution. All
branches, jumps, subroutine calls, returns, and status register manipulations
can be traced in this way. No exception occurs if a branch is not taken.
When T[1 :0]
=
10 at the beginning of instruction execution, a trace exception will •
be generated when execution is complete. If the instruction is not executed,
either because an interrupt is taken or because the instruction is illegal,
unimplemented, or privileged, an exception is not generated.
At the present time, T[1 :0]
=
11 is an undefined condition. It is reserved by
Motorola for future use.
Exception processing for trace starts at the end of normal processing for the
traced instruction and before the start of the next instruction. Exception
processing follows the regular sequence (tracing is disabled so that the trace
exception itself is not traced). A vector number is generated to reference the
trace exception vector. The address of the instruction that caused the trace
exception, the trace exception vector offset, the current program counter, and a
copy of the status register are saved on the supervisor stack. The saved value
of the program counter is the address of the next instruction to be executed.
CPU32 REFERENCE MANUAL
"EXCEPTION PROCESSING MOTOROLA
6-13