Low-Power Stop Instruction; Processing States; Privilege States - Motorola CPU32 Reference Manual

1.1.6.2 Low-Power Stop Instruction
The CPU32 is a fully static design. Power consumption can be reduced to a •
minimum during periods of inactivity by stopping the system clock. The CPU32
instruction set includes a low-power stop command (LPSTOP) that efficiently
implements this capability. The processor will remain in stop mode until a user-
specified interrupt, or reset, occurs.
1.1.7 Processing States
There are four processing states - normal, exception, background and halted.
Normal processing is associated with instruction execution. The bus is used to
fetch instructions and operands, and to store results.
Exception processing is associated with interrupts, trap instructions, tracing, and
other exception conditions.
Background processing allows interactive debugging of the system.
Halted processing is an indication of catastrophic hardware failure.
See SECTION 5 PROCESSING STATES for complete information.
1.1.8 Privilege States
The processor can operate at either of two privilege levels. Supervisor level is
more privileged than user level - all instructions are available at supervisor
level, but access is restricted at user level.
Effective use of privilege level can protect system resources from uncontrolled
access. The state of the S bit in the status register determines access level and
whether the user stack pointer (USP) or the supervisor stack pointer (SSP) is
used for stack operations.
See SECTION 5 PROCESSING STATES for a complete explanation of
privilege levels.
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