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seCD
Operation:
Assembler
Syntax:
Attributes:
Subtract Decimal with Extend
Destination10 - SourcelO - X
=>
Destination
SBCD Dx, Dy
SBCD -(Ax), -(Ay)
Size
=
(Byte)
seCD
Description:
Subtracts the source operand and the extend bit from the destination operand and
stores the result in the destination location. The subtraction is performed using binary coded
decimal arithmetic; the operands are packed BCD numbers. The instruction has two modes:
1.
Data register to data register: The data registers specified by the instruction contain the
operands.
2.
Memory to memory:
The address registers specified by the instruction access the
operands from memory using the predecrement addressing mode.
Condition Codes:
x
N
z
v
u
u
X Set the same as the carry bit.
N Undefined.
c
Z Cleared if the result is nonzero. Unchanged otherwise.
V Undefined.
C Set if a borrow (decimal) is generated. Cleared otherwise.
NOTE
Normally the Z condition code bit is set via programming before the start of an
operation. This allows successful tests for zero results upon completion of
multiple-precision operations.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2 1 0
o
o
o
REGISTER Ry
o
o
o
o
I
RIM
I
REGISTERRx
Instruction Fields:
Register Dy/Ay field - Specifies the destination register.
If RIM
=
0, specifies a data register.
If RIM
=
1, specifies an address register for the predecrement addressing mode.
RIM field - Specifies the operand addressing mode:
° -
The operation is data register to data register.
1 - The operation is memory to memory.
Register Dx/Ax field - Specifies the source register:
If RIM
=
0,
specifies a data register.
If RIM
=
1, specifies an address register for the predecrement addressing mode.
CPU32 REFERENCE MANUAL
INSTRUCTION SET
MOTOROLA
4-145
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